cystech electronics corp. spec. no. : c351y3 issued date : 2011.08.24 revised date : page no. : 1/6 DTC114EY3 cystek product specification npn digital transistors ( built-in resistors ) DTC114EY3 features ? built-in bias resistors enable the configuration of an inverter circu it without connecting external input resistors (see equi valent circuit). ? the bias resistors consist of thin -film resistors with complete isolat ion to allow negative biasing of the input. they also have the advantage of almost completely eliminating parasitic effects. ? only the on/off conditions need to be set for operation, making device design easy. ? complements the dta114ey3 ? pb-free package equivalent circuit outline sot-723 DTC114EY3 r1=10k , r2=10 k collector(out) in(b) : base out(c) : collector gnd(e) : emitter base(in) emitter(gnd) absolute maximum ratings (ta=25 c) parameter symbol limits unit supply voltage v cc 50 v input voltage v i -10~+40 v i o 50 ma output current i o(max.) 100 ma power dissipation pd 150 mw junction temperature tj 150 c storage temperature tstg -55~+150 c
cystech electronics corp. spec. no. : c351y3 issued date : 2011.08.24 revised date : page no. : 2/6 DTC114EY3 cystek product specification electrical characteristics (ta=25 c) parameter symbol min. typ. max. unit test conditions v i(off) - - 0.5 v v cc =5v, i o =100 a input voltage v i(on) 3 - - v v o =0.3v, i o =10ma output voltage v o(on) - - 0.3 v i o /i i =10ma/0.5ma input current i i - - 0.88 ma v i =5v output current i o(off) - - 0.5 a v cc =50v, v i =0v dc current gain g i 30 - - - v o =5v, i o =5ma input resistance r 1 7 10 13 k - resistance ratio r 2 /r 1 0.8 1 1.2 - - transition frequency f t - 250 - mhz v ce =10v, i c =5ma, f=100mhz * * transition frequency of the device ordering information device package shipping marking DTC114EY3 sot-723 (pb-free) 8000 pcs / tape & reel 8a
cystech electronics corp. spec. no. : c351y3 issued date : 2011.08.24 revised date : page no. : 3/6 DTC114EY3 cystek product specification typical characteristics current gain vs output current 10 100 1000 1 10 100 output current ---io(ma) current gain---g i vo=5v output voltage vs output current 10 100 1000 1 10 100 output current ---io(ma) output voltage---v o(on) (mv) io / ii=20 input voltage vs output current (on characteristics) 1 10 0.1 1 10 100 output current --- io(ma) input voltage --- v i(on) (v) vo=0.3v output current vs input voltage (off characteristics) 0.1 1 10 100 0.1 1 10 input voltage --- v i(off) (v) output current --- io(ma) vcc=5v power derating curve 0 20 40 60 80 100 120 140 160 0 50 100 150 200 ambient temperature---ta(c) power dissipation---pd(mw)
cystech electronics corp. spec. no. : c351y3 issued date : 2011.08.24 revised date : page no. : 4/6 DTC114EY3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c351y3 issued date : 2011.08.24 revised date : page no. : 5/6 DTC114EY3 cystek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c351y3 issued date : 2011.08.24 revised date : page no. : 6/6 DTC114EY3 cystek product specification sot-723 dimension *typical millimeters inches millimeters inches dim min. max. min. max. marking: 8a 3-lead sot-723 plastic surface mounted package cystek package code: y3 style: pin 1.base(in) 2.emitter(gnd) 3.collector(out) dim min. max. min. max. a 0.000 0.500 0.000 0.020 d 1.150 1.250 0.045 0.049 a1 0.000 0.050 0.000 0.002 e 1.150 1.250 0.045 0.049 b 0.170 0.270 0.007 0.011 e1 0.750 0.850 0.030 0.033 b1 0.270 0.370 0.011 0.015 e 0.800* 0.031* c 0.000 0.150 0.000 0.006 7 ref 7 ref notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
|
